The present invention relates generally to a method and apparatus for calculating delay times in a semiconductor circuit. More particularly, the present invention relates to a delay time calculating method and apparatus suitable for use in logic simulation, combination and timing analysis during a design phase of a custom LSI or semi-custom integrated circuit device.
Increasing the integration scale of semiconductor devices results in a longer time for performing logic simulation or the like of logic circuits. In order to shorten the design time, therefore, it is important to decrease logic design and test time for semiconductor devices.
One of the tools to test whether a semiconductor device is designed as specified is timing simulation. The timing simulation performs logic circuit simulation in light of the delay times of the interconnection and individual circuits (gates, cells, etc.) of a semiconductor device, and inspects the circuit timings, such as the occurrence of hazards, under conditions close to actual circuit operations. The timing simulation uses a tool (delay time calculating apparatus) for estimating the delay time of a semiconductor device. The delay time calculating apparatus estimates the delay time of a semiconductor device using design data (logic circuit data, layout pattern data, etc.) of the semiconductor device.
The delay time of a semiconductor device depends on, or is affected by, factors (dependency factors) such as the supply voltage supplied to the semiconductor device, the fabrication process and the temperature of the semiconductor device while in use. The delay time calculating apparatus estimates the delay time in accordance with the dependency factors. Timing simulation is executed in accordance with the estimated delay time to inspect the operational timing of the semiconductor device.
To reduce the power dissipation of a system, a semiconductor device which operates on a relatively low supply voltage may be used. When a semiconductor device which operates on a low voltage and a semiconductor device which operates on a voltage higher than the low voltage are present in the same system, however, a high voltage signal may be supplied to the low-voltage semiconductor device. In this case, a low-voltage semiconductor device which is compatible both with a high supply voltage (first operational supply voltage) and a low supply voltage (second operational supply voltage) is provided. Specifically, the semiconductor device includes an internal circuit which operates on a low voltage and an interface circuit which converts the voltage of an external signal (high voltage) to a low voltage suitable for the internal circuit. When operational supply voltages of 2.5 V and 3 V are supplied to a semiconductor device, for example, the internal circuit operates on 2.5 V. The interface circuit converts an external input signal having an amplitude of 3 V to a signal having an amplitude of 2.5 V, and transmits the converted signal to the internal circuit. The interface circuit also converts a signal of 2.5 V to a signal of 3 V. Similarly, in a semiconductor device designed according to another specification which is compatible with 2 V and 2.8 V, the interface circuit converts a signal having an amplitude of 2.8 V to a signal having an amplitude of 2 V.
The delay time of a semiconductor circuit device is relatively short for a high supply voltage device and relatively long for a low supply voltage device. The delay time calculating apparatus has delay time data which is prepared on the basis of dependency factors like the supply voltage, fabrication process and temperature in use. Referring to FIG. 1, for each circuit element, the delay time data has a matrix table 71 having dimensions which correspond to the number of dependency factors. The matrix table 71 is used to store delay time ratios for various conditions. For example, when the dependency factors of one circuit element are a process condition, a temperature in use and two operational supply voltages V1 and V2, the matrix table 71 is designed as four-dimensional. Specifically, the matrix table 71 includes a plurality of three-dimensional matrix tables 73 of the process condition, the operational supply voltage V1 and the temperature in use. Each three-dimensional matrix table 73 corresponds to a respective operational supply voltage V2 as a fourth dependency factor. That is, each three-dimensional matrix table 73 includes a plurality of two-dimensional tables 72 of the process condition and the operational supply voltage V1 based on the respective operational supply voltage V2.
The value of each delay time ratio stored in the matrix table 71 represents the ratio acquired by dividing a delay time under the condition of the several dependency factors by a reference delay time under the reference condition. The reference delay time is a delay time set under predetermined circuit usage conditions of the semiconductor device. The delay time is calculated as follows. First, the value of one delay time ratio corresponding to a given circuit use condition is acquired from the matrix table 71. Then, the value of the delay time ratio is multiplied by the reference delay time, yielding a delay time of a circuit element under a given circuit use condition. Such delay time is calculated for each circuit of the semiconductor device. The timing of the semiconductor device is then checked using the calculated delay times.
Increasing the number of dependency factors of a circuit element results in an increase in the number of matrix tables. For example, ten two-dimensional matrix tables 72 are needed for three dependency factors, whereas one hundred two-dimensional matrix tables 72 are required for four dependency factors when the number of each of dependency factors is ten. The increased number of matrix tables therefore leads to a longer time for computing the delay time under circuit use conditions, which increases the time required to check the device timing.
Recently, a high-performance personal computer is provided. However, a memory device, such as a hard disk of the personal computer can not entirely store data when the quantity of data is increased, so that it is impossible to use the personal computer.
Accordingly, it is an object of the present invention to provide a delay time calculating method and apparatus which does not unduly increase the amount of data used in the computation of a delay time.
Briefly stated, the invention provides a method of computing delay times of circuit elements of a semiconductor device. The method includes the following operations: preparing at least one coefficient table storing a plurality of delay time ratio coefficient values thereon, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element; acquiring the delay time ratio coefficient value associated with at least one of the plurality of dependency factors from the coefficient table; and computing a delay time of a circuit element using the acquired delay time ratio coefficient value and a reference delay time.
The present invention provides an apparatus for computing delay times of circuit elements of a semiconductor device. The apparatus includes the following elements: at least one coefficient table storing a plurality of delay time ratio coefficient values, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element; and a processing unit for acquiring a delay time ratio coefficient value associated with at least one of the plurality of dependency factors from the coefficient table, and computing a delay time of a circuit element using the acquired delay time ratio coefficient value and a reference delay time.
The present invention provides a method of generating a coefficient table for use in computing delay times of circuit elements of a semiconductor device. The method includes the following operations: computing a plurality of delay time ratio coefficient values, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element; and storing the plurality of delay time ratio coefficient values in the coefficient table.
The present invention provides a storage product including a recording medium where a computer readable program code for computing delay times of circuit elements of a semiconductor device is recorded thereon. The program executes the following operations: preparing at least one coefficient table storing a plurality of delay time ratio coefficient values, each of the delay time ratio coefficient values representing a ratio of a delay time determined by values of a plurality of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element; acquiring the delay time ratio coefficient value associated with at least one of the plurality of dependency factors from the coefficient table; and computing a delay time of a circuit element using the acquired delay time ratio coefficient value and a reference delay time.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.